1. Field of the Invention
The invention pertains to the field of fabrication of MNOS and MOS memory devices.
2. The Prior Art
The manner of functioning of a MNOS memory transistor (MNOS=metal-nitride-oxide-semiconductor) depends on the fact that, in an MNOS field effect transistor, the conduction state or, respectively, the threshold voltage of the transistor defined for a prescribed gate voltage is permanently changed by means of spatially stationary charges in the gate double insulation layer or, respectively, in the silicon nitride layer. In programming, negative charges are deposited in the addressed transistors at the boundary surface nitride-oxide or, respectively, in the nitride by means of a voltage pulse, said charges making these transistors permanently blocking. The charges can subsequently be removed by means of a pulse of reverse polarity or by means of other cancelling methods. Another method is "short channel cancelling" in which a positive voltage pulse is applied to the source and drain region, whereas the substrate and gate lie at grounded potential.
The manufacture of a Very Large Scale Integrated (VLSI) circuit requires thin gate oxides (smaller than 0.05 .mu.m). As a result of this demand, the avalanche breakdown voltage at the pn junction on the drain side is reduced. For the short channel cancelling of silicon dioxide/silicon nitride double insulator layer memory elements (MNOS transistors), the cancellation operation (avalanche punch-through breakdown) is rendered more difficult, since the transistors already punch through before the extinction voltage at the pn junctions of the source-drain region is reached.
Self-adjusting methods are sought for the reduction of the tolerances and, thus, for shortening the channel length. Such a method for the manufacture of a MNOS memory cell can be derived from the patent application, U.S. Ser. No. 146,392 (corresponding to German Patent Application P No. 29 18 888.3). Thereby, the effective channel length is adjusted in that the gate electrode is subdivided into two differently drivable, mutually superimposed electrodes (dual gate) and the connection of the gate electrodes is produced via self-adjusting, overlapping contacts. With respect to the plane of the substrate surface, the edges of the second gate electrode lying over the first gate electrode (memory gate) lie perpendicular and self-adjusting over the edges of the source and drain zone. The memory nitride layer extends beyond the area of the channel zone, partially to the source and drain zone.
A method is also known from the prior art (/1/ I. Ohkura et al, Proceedings of the 8th Conference on Solid State Dev., Tokyo 1976, Jap. J. Applied Physics Supplement, 16, 167-171 (1977); /2/ I. Ohkura et al, IEEE Transactions on Electronic Devices, ED-26, 43-435 (1979)) for the manufacture of normal transistors of short channel length in VLSI technology with self-adjusting, double-diffused source-drain regions.